Authors: Ming‐Jin Liu, Wei‐Jie Lan, Cai‐Syuan Huang, Chang‐Zhi Chen, Ruei‐Hong Cyu, Paul Albert L. Sino, Yu‐Lun Yang, Po‐Wen Chiu, Feng‐Chuan Chuang, Chang‐Hong Shen, Jyun‐Hong Chen, Yu‐Lun Chueh
Published: 2024-01-24
Source: Full article
AbstractHerein, the structure of integrated M3D inverters are successfully demonstrated where a chemical vapor deposition (CVD) synthesized monolayer WSe2 p‐type nanosheet FET is vertically integrated on top of CVD synthesized monolayer MoS2 n‐type film FET arrays (2.5 × 2.5 cm) by semiconductor industry techniques, such as transfer, e‐beam evaporation (EBV), and plasma etching processes. A low temperature (below 250 °C) is employed to protect the WSe2 and MoS2 channel materials from thermal decomposition during the whole fabrication process. The MoS2 NMOS and WSe2 PMOS device fabricated show an on/off current ratio exceeding 106 and the integrated M3D inverters indicate an average voltage gain of ≈9 at VDD = 2 V. In addition, the integrated M3D inverter demonstrates an ultra‐low power consumption of 0.112 nW at a VDD of 1 V. Statistical analysis of the fabricated inverters devices shows their high reliability, rendering them suitable for large‐area applications. The successful demonstration of M3D inverters based on large‐scale 2D monolayer TMDs indicate their high potential for advancing the application of 2D TMDs in future integrated circuits.